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PROCEOSOR ZA LAPTOPOVE Intel Pentium B960


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Proizvođač: Intel

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SR07V (Intel Pentium B960)

SR07V specifications
General information

Type CPU / Microprocessor
Family Intel Pentium Dual-Core Mobile
Processor number ? B960
Part number FF8062700997701
Frequency (GHz) ? 2.2
Clock multiplier ? 22
Package type 988-pin micro-FCPGA
Socket type Socket G2 (rPGA988B)

Architecture / Microarchitecture / Other

Core stepping Q0
Processor core Sandy Bridge
Manufacturing technology (micron) 0.032
Number of cores 2
L3 cache size (MB) 2
Features EM64T technology ?
Enhanced SpeedStep technology ?
Execute disable bit ?
Case temperature (°C) ? 85
Thermal Design Power (Watt) ? 35

Notes on sSpec SR07V


Integrated graphics controller runs at 650 MHz.
The part supports DDR3-1066 and DDR3-1333 memory.
Frequency of integrated graphics controller in turbo mode is 1100 MHz.
Direct Memory Interface speed is 5 GT/s.


Related S-Spec numbers

In addition to the SR07V S-Spec, this processor was also manufactured with one pre-production S-Spec number:
Stepping S-Spec FF8062700997701
D2 QACL +
Q0 SR07V +

NOTE: Engineering and qualifications samples are marked with this color
SR07V CPUID information
View / search public CPUID submissions
Intel Pentium Dual-Core Mobile B960 SR07V
Part number: FF8062700997701
Frequency: 2200 MHz

Comment:
Submitted by: CPU-World

General information
Vendor: GenuineIntel
Processor name (BIOS): Intel(R) Pentium(R) CPU B960 @ 2.20GHz
Cores: 2
Logical processors: 2
Processor type: Original OEM Processor
CPUID signature: 206A7
Family: 6 (06h)
Model: 42 (02Ah)
Stepping: 7 (07h)
TLB/Cache details: 64-byte Prefetching
Data TLB0: 2-MB or 4-MB pages, 4-way set associative, 32 entries
Data TLB: 4-KB Pages, 4-way set associative, 64 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L2 TLB: 1-MB, 4-way set associative, 64-byte line size
Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries

Cache: L1 data L1 instruction L2 L3
Size: 2 x 32 KB 2 x 32 KB 2 x 256 KB 2 MB
Associativity: 8-way set
associative 8-way set
associative 8-way set
associative 8-way set
associative
Line size: 64 bytes 64 bytes 64 bytes 64 bytes
Comments: Direct-mapped Direct-mapped Non-inclusive
Direct-mapped Inclusive
Shared between all cores

Instruction set extensions Additional instructions
MMX CLFLUSH
SSE CMOV
SSE2 CMPXCHG16B
SSE3 CMPXCHG8B
SSSE3 FXSAVE/FXRSTORE
SSE4.1 MONITOR/MWAIT
SSE4.2 PCLMULDQ
POPCNT
RDTSCP
SYSENTER/SYSEXIT
XSAVE / XRESTORE states

Major features Other features
On-chip Floating Point Unit 36-bit page-size extensions
64-bit / Intel 64 64-bit debug store
NX bit/XD-bit Advanced programmable interrupt controller
Enhanced SpeedStep CPL qualified debug store
Debug store
Debugging extensions
Digital Thermal Sensor capability
Extended xAPIC support
LAHF / SAHF support in 64-bit mode
Machine check architecture
Machine check exception
Memory-type range registers
Model-specific registers
Page attribute table
Page global extension
Page-size extensions (4MB pages)
Pending break enable
Perfmon and Debug capability
Physical address extensions
Power Limit Notification capability
Process context identifiers
Self-snoop
TSC rate is ensured to be invariant across all states
Thermal monitor
Thermal monitor 2
Thermal monitor and software controlled clock facilities
Time stamp counter
Timestamp counter deadline
Virtual 8086-mode enhancements
xTPR Update Control


Predmet: 29841597